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FSCM0765R
Features
Green Mode Fairchild Power Switch (FPSTM)
* Internal Avalanche Rugged Sense FET * Low startup current (max 40uA) * Low power consumption under 1 W at 240VAC & 0.4W load * Precise Fixed Operating Frequency (66kHz) * Frequency Modulation for low EMI * Pulse by Pulse Current Limiting (Adjustable) * Over Voltage Protection (OVP) * Over Load Protection (OLP) * Thermal Shutdown Function (TSD) * Auto-Restart Mode * Under Voltage Lock Out (UVLO) with hysteresis * Built-in Soft Start (15ms) Table 1. Maximum Output Power OUTPUT POWER TABLE
230VAC 15%(3) PRODUCT FSCM0565RD FSCM0765RD FSCM0565RC FSCM0765RC Adapter(1) 50W 65W 70W 85W Open Frame(2) 65W 70W 85W 95W 85-265VAC Adapter(1) 40W 50W 60W 70W Open Frame(2) 50W 60W 70W 85W
Application
* SMPS for VCR, SVR, STB, DVD & DVCD * Adaptor * SMPS for LCD Monitor
Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient. 2. Maximum practical continuous power in an open frame design at 50C ambient. 3. 230 VAC or 100/115 VAC with doubler.
Description
The FSCM0765R is an integrated Pulse Width Modulator (PWM) and Sense FET specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high voltage power switching regulator which combine an avalanche rugged Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of flyback converters.
Typical Circuit
DC OUT AC IN
Drain
PWM
Ilimit Vfb Vcc GND
Figure 1. Typical Flyback Application
Rev.1.0.0
(c)2004 Fairchild Semiconductor Corporation
FSCM0765R
Internal Block Diagram
Vcc 3 Vcc good 0.3/0.5V
+
Drain 1 Vref Internal Bias
8V/12V
Freq. Modulation OSC
Vcc Idelay Vcc IFB
PWM 2.5R
S R
Q Q
FB 4 Ilimit 5
R
0.3K Soft start
Gate driver LEB
VSD Vcc
S Q Q
2 GND
Vovp TSD Vcc UV reset Vcc good
R
Figure 2. Functional Block Diagram of FSCM0765R
2
FSCM0765R
Pin Definitions
Pin Number 1 2 3 Pin Name Drain GND Vcc Pin Function Description This pin is the high voltage power SenseFET drain. It is designed to drive the transformer directly. This pin is the control ground and the SenseFET source. This pin is the positive supply voltage input. Initially, During start up, the power is supplied through the startup resistor from DC link. When Vcc reaches 12V, the power is supplied from auxiliary transformer winding. This pin is internally connected to the inverting input of the PWM comparator. The collector of an optocoupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6.0V, the over load protection is activated resulting in shutdown of the FPS. This pin is for the pulse by pulse current limit level programming. By using a resistor to GND on this pin, the current limit level can be changed. If this pin is left floating, the typical current limit will be 3.0A.
4
Feedback (FB)
5
I_limit
Pin Configuration
FSCM0765RD D2-PAK-5L
FSCM0765RC TO-220-5L
FSCM0765RD
1 : Drain
FSCM0765RC
5 : I_limit 4 : FB 3 : Vcc 2 : GND
5. I_limit 4. FB 3. Vcc 2. GND 1. Drain
Figure 3. Pin Configuration (Top View)
3
FSCM0765R
Absolute Maximum Ratings
(Ta=25C, unless otherwise specified) Parameter Drain-Source (GND) Voltage Gate-Source (GND) Voltage Drain Current Pulsed Avalanch Current
(4) (2) (1)
Symbol VDSS VDGR VGS IDM EAS IAS ID ID VCC VFB PD Derating PD Derating TJ TA TSTG
Value 650 650 30 28 370 35 7 4.5 20 -0.3 to VCC 83 0.018 145 1.163 Internally limited -25 to +85 -55 to +150
Unit V V V ADC mJ A ADC ADC V V W W/C W W/C C C C
Drain-Gate Voltage (RGS=1M)
Single Pulsed Avalanch Energy (3) Continuous Drain Current (Tc = 25C) Continuous Drain Current (TC=100C) Supply Voltage Analog Input Voltage Range Total Power Dissipation (D2-PAK) Total Power Dissipation (TO-220) Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range
Notes: 1. Tj = 25C to 150C 2. Repetitive rating: Pulse width limited by maximum junction temperature 3. L = 30mH, VDD = 50V, RG = 25, starting Tj = 25C 4. L = 13uH, starting Tj = 25C
4
FSCM0765R
Electrical Characteristics
(Ta = 25C unless otherwise specified) Parameter Sense FET SECTION Drain source breakdown voltage Zero gate voltage drain current Static drain source on resistance Output capacitance Turn on delay time Rise time Turn off delay time Fall time CONTROL SECTION Initial frequency Modulated frequency range Frequency modulation cycle Voltage stability Temperature stability Maximum duty cycle Minimum duty cycle Start threshold voltage Stop threshold voltage Feedback source current Soft-start time Leading Edge Blanking time BURST MODE SECTION Burst Mode Voltages VBH VBL Vcc=14V Vcc=14V 0.4 0.24 0.5 0.3 0.6 0.36 V V FOSC Fmod Tmod FSTABLE FOSC DMAX DMIN VSTART VSTOP IFB TSS TLEB VFB=GND VFB=GND VFB=GND VCC=14V, VFB=4V 10VVCC17V -25CTa+85C 60 0 75 11 7 0.7 10 66 3 4 1 5 80 12 8 0.9 15 300 72 3 10 85 0 13 9 1.1 20 kHz kHz ms % % % % V V mA ms ns BVDSS IDSS RDS(ON) COSS TD(ON) TR TD(OFF) TF VGS = 0V, ID = 250A VDS = Max, Rating VGS = 0V VGS = 10V, ID = 2.3A VGS = 0V, VDS = 25V, f = 1MHz VDD= 325V, ID= 5A (MOSFET switching time is essentially independent of operating temperature) 650 1.4 100 25 60 115 65 500 1.6 ns V A
Symbol
Condition
Min.
Typ.
Max.
Unit
pF
5
FSCM0765R
PROTECTION SECTION Peak current limit Over voltage protection Thermal shutdown temperature Shutdown delay current Shutdown feedback voltage TOTAL DEVICE SECTION Startup current Istart IOP Operating supply current IOP(MIN) IOP(MAX) VFB=GND, VCC=17V 2.5 5 mA 20 40 A ILIM VOVP TSD IDELAY VSD VFB=5V VFB>5.5V VCC=14V, VFB=4V 2.64 18 130 3.5 5.5 3 19 145 5.3 6 3.36 20 160 7 6.5 A V C A V
Notes: 1. Pulse test : Pulse width 300S, duty 2% 2. These parameters, although guaranteed at the design, are not tested in mass production. 3. These parameters, although guaranteed, are tested in EDS (wafer test) process. 4. These parameters indicate the inductor current. 5. This parameter is the current flowing into the control IC.
6
FSCM0765R
Comparison Between FSDM07652R and FSCM0765R
Function Frequency modulation N.A. FSDM07652R FSCM0765R Available * Modulated frequency range (DFmod) = 3kHz * Frequency modulation cycle (Tmod) = 4ms * Programmable using external resistor (3.0A max) * N.A. (Requires startup resistor) * Startup current : 40uA (max)
Pulse-by-pulse current limit * Internally fixed (2.5A) Internal Startup Circuit * Available
7
FSCM0765R
Typical Performance Characteristics
(These Characteristic Graphs are Normalized at Ta= 25C)
1.60 1.40 Start up Current (Normalized to 25) 1.20 1.00 0.80 0.60 -50 -25 0 25 50 75 100 Junction Temperature() 125
1.20 1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 125 Junction T emperature( )
Startup Current vs. Temp
10 .2 12 .1 14 .0 06 .9 08 .8 00 .8 -5 0 -2 5 0 2 5 5 0 7 5 10 0 15 2 Ju ctio T p re( n n emeratu )
Start Threshold Voltage (Normalized to 25)
Start Threshold Voltage vs. Temp
1.20 Initial Frequency (Normalized to 25) 1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 125 Junction Temperature()
Stop Threshold Voltag (Normalized to 25 )
Stop Threshold Voltage vs. Temp
Initial Freqency vs. Temp
1.20 Maximum Duty Cycle (Normalized to 25)
FB Source Current (Normalized to 25)
1.20 1.12 1.04 0.96 0.88 0.80
1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 125 Junction Temperature()
-50
-25
0
25
50
75
100
125
Junction Temperature()
Maximum Duty Cycle vs. Temp
Feedback Source Current vs. Temp
8
FSCM0765R
Typical Performance Characteristics (Continued)
(These Characteristic Graphs are Normalized at Ta= 25C)
1.20 1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 Junction Temperature() 125 Shutdown Delay Current (Normalized to 25) Shutdown FB Voltage (Normalized to 25)
1.20 1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 125 Junction Temperature()
ShutDown Feedback Voltage vs. Temp
ShutDown Delay Current vs. Temp
1.20
Burst Mode Disable Voltage (Normalized to 25)
1.20 1.12 1.04 0.96 0.88 0.80
Burst Mode Enable Voltage (Normalized to 25)
1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 125 Junction Temperature()
-50
-25
0
25
50
75
100
125
Junction Temperature()
Bust Mode Enable Volage vs. Temp
Burst Mode Disable Voltage vs. Temp
1.20 Operating Supply Current (Normalized to 25) 1.12 1.04 0.96 0.88 0.80
1.20 Maximum Drain Current (Normalized to 25) 1.12 1.04 0.96 0.88 0.80 -50 -25 0 25 50 75 100 125 Junction T emperature()
-50
-25
0
25
50
75
100
125
Junction Temperature()
Mavimum Drain Current vs. Temp
Operating Supply Current vs. Temp
9
FSCM0765R
Typical Performance Characteristics (Continued)
(These Characteristic Graphs are Normalized at Ta= 25C)
1.2 1.0 Soft Start Time (Normalized to 25) 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 125 Junction Temperature ()
Soft Start Time vs. Temp
10
FSCM0765R
Functional Description
1. Startup : Figure 4 shows the typical startup circuit and transformer auxiliary winding for FSCM0765R application. Before FSCM0765R begins switching, FSCM0765R consumes only startup current (typically 25uA) and the current supplied from the DC link supply ccurrent consumed by FPS (Icc) and charges the external capacitor (Ca) that is connected to the Vcc pin. When Vcc reaches start voltage of 12V (VSTART), FSCM0765R begins switching, and the current consumed by FSCM0765R increases to 3mA. Then, FSCM0765R continues its normal switching operation and the power required for this device is supplied from the transformer auxiliary winding, unless Vcc drops below the stop voltage of 8V (VSTOP). To guarantee the stable operation of the control IC, Vcc has under voltage lockout (UVLO) with 4V hysteresis. Figure 5 shows the relation between the current consumed by FPS (Icc) and the supply voltage (Vcc).
The minimum current supplied through the startup resistor is given by
min min
I sup
= ( 2 V line
- V start ) -----------
1 R str
where Vlinemin is the minimum input voltage, Vstart is the start voltage (12V) and Rstr is the startup resistor. The startup resistor should be chosen so that Isupmin is larger than the maximum startup current (40uA). If not, Vcc can not be charged to the start voltage and FPS will fail to start up.
C DC
2. Feedback Control : FSCM0765R employs current mode control, as shown in Figure 6. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased.
AC line (V linemin - V linemax)
Isup
Rstr Da
Vcc
FSCM0765R
Icc Ca
Figure 4. Startup circuit
2.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is determined by the inverting input of PWM comparator (Vfb*) as shown in Figure 6. When the current through the opto transistor is zero and the current limit pin (#5) is left floating, the feedback current source (IFB) of 0.9mA flows only through the internal resistor (R+2.5R=2.8k). In this case, the cathode voltage of diode D2 and the peak drain current have maximum values of 2.5V and 3A, respectively. The pulse-by-pulse current limit can be adjusted using a resistor to GND on current limit pin (#5). The current limit level using an external resistor (RLIM) is given by
R LIM 3A I LIM = -----------------------------------2.8k + R LIM
Icc
Vcc Idelay
Vref IFB 0.9mA
OSC
3mA
Vo
Vfb
H11A817A
CB
4 D1 0.3k + Vfb* D2 2.5R
SenseFET
Power Down 25uA Vstop=8V
Power Up
KA431
R
Gate driver
5 RLI M
-
Vcc Vstart=12V Vz
Figure 5. Relation between operating supply current and Vcc voltage
VSD
OLP
Rsense
Figure 6. Pulse width modulation (PWM) circuit
11
FSCM0765R
2.2 Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSCM0765R employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. 3. Protection Circuit : The FSCM0765R has several self protective functions such as over load protection (OLP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage of 8V, the current consumed by FSCM0765R reduces to the startup current (typically 25uA) and the current supplied from the DC link charges the external capacitor (Ca) that is connected to the Vcc pin. When Vcc reaches the start voltage of 12V, FSCM0765R resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 7).
even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 5.3uA current source (Idelay) starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is terminated as shown in Figure 8. The delay time for shutdown is the time required to charge CB from 2.5V to 6.0V with 5.3uA (Idelay). In general, a 10 ~ 50 ms delay time is typical for most applications.
V FB Over load protection
6.0V
Vds
Power on
Fault occurs
2.5V
Fault removed
T12= Cfb*(6.0-2.5)/Idelay
T1
T2
t
Figure 8. Over load protection
Vcc
12V 8V
t
Normal operation Fault situation Normal operation
Figure 7. Auto restart operation
3.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However,
3.2 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FSCM0765R uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V.
12
FSCM0765R
3.3 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 145C, the thermal protection is triggered resulting in shutdown of FPS. 4. Frequency Modulation : EMI reduction can be accomplished by modulating the switching frequency of a switched power supply. Frequency modulation can reduce EMI by spreading the energy over a wider frequency range than the band width measured by the EMI test equipment. The amount of EMI reduction is directly related to the depth of the reference frequency. As can be seen in Figure 9, the frequency changes from 63KHz to 69KHz in 4ms.
device automatically enters into burst mode when the feedback voltage drops below VBL (300mV). At this point switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBH (500mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in standby mode.
Vo
Voset
VFB
Drain current
0.5V 0.3V
Ts
Ids
Ts
Vds
Ts fs
69kHz 66kHz 63kHz
time
T1
Switching disabled
T2 T3
Switching disabled
T4
Figure 10. Waveforms of burst operation
4ms
t
Figure 9. Frequency Modulation
5. Soft Start : The FSCM0765R has an internal soft start circuit that increases PWM comparator inverting input voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 15msec, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, rectifier diodes and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 6. Burst operation : In order to minimize power dissipation in standby mode, the FSCM0765R enters into burst mode operation at light load condition. As the load decreases, the feedback voltage decreases. As shown in Figure 10, the 13
FSCM0765R
Typical application circuit
Application LCD Monitor Output power 40W Input voltage Universal input (85-265Vac) Output voltage (Max current) 5V (2.0A) 12V (2.5A)
Features
* * * * * * High efficiency (>81% at 85Vac input) Low standby mode power consumption (<1W at 240Vac input and 0.4W load) Low component count Enhanced system reliability through various protection functions Low EMI through frequency modulation Internal soft-start (15ms)
Key Design Notes
* Resistors R102 and R105 are employed to prevent start-up at low input voltage * The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is required, C106 can be reduced to 22nF. 1. Schematic
D202 T1 EER3016 MBRF10100 R102 500k R103 56k 2W C104 2.2nF 1kV R105 D101 500k UF 4007 1 10 C201 1000uF 25V
L201 12V, 2.5A C202 1000uF 25V
2
8
C103 100uF 400V BD101 2 2KBP06M3N257 1 3 R106 5k 1/4W 4 C102 220nF 275VAC C106 47nF 50V
3
FSCM0765RC 5 Ilimit Drain 1 D201 MBRF1045 C105 D102 22uF TVR10G 50V R104 5 4 7 C203 1000uF 10V L202 5V, 2A C204 1000uF 10V
4
Vcc 3 Vfb GND 2
ZD101 22V
5
6
LF101 23mH
C301 4.7nF
R201 1k R101 560k 1W IC301 H11A817A R204 5.6k R203 10k C205 47nF
R202 1.2k
RT1 5D-9
C101 220nF 275VAC
F1 FUSE 250V 2A
IC201 KA431
R205 5.6k
14
FSCM0765R
2. Transformer Schematic Diagram
EER3016 Np/2 Np/2 1 2 3 4 Na 5
3.Winding Specification
10 N 9 8 7 6
12V
N5V
No Na Np/2 N12V N5V Np/2
Pin (sf) 45 21 10 8 76 32
Wire 0.2 x1
Turns 8 18 7 3 18
Winding Method Center Winding Solenoid Winding Center Winding Center Winding Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers 0.4 x 1 0.3 x 3 0.3 x 3 0.4 x 1 Insulation: Polyester Tape t = 0.050mm, 2Layers Insulation: Polyester Tape t = 0.050mm, 2Layers Insulation: Polyester Tape t = 0.050mm, 2Layers Outer Insulation: Polyester Tape t = 0.050mm, 2Layers
4.Electrical Characteristics
Pin Inductance Leakage Inductance 1-3 1-3
Specification 520uH 10% 10uH Max
Remarks 100kHz, 1V 2nd all short
5. Core & Bobbin Core : EER 3016 Bobbin : EER3016 Ae(mm2) : 96
15
FSCM0765R
6.Demo Circuit Part List
Part F101 RT101 R101 R102 R103 R104 R105 R106 R201 R202 R203 R204 R205
Value Fuse 2A/250V NTC 5D-9 Resistor 560K 500K 56K 5 500K 5K 1K 10K 1.2K 5.6K 5.6K Capacitor
Note
Part C301
Value 4.7nF Inductor
Note Polyester Film Cap.
L201 L202 1W 1/4W 2W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W BD101 D101 D102 D201 D202
5uH 5uH
Wire 1.2mm Wire 1.2mm
Diode UF4007 TVR10G MBRF1045 MBRF10100
Bridge Diode 2KBP06M 3N257 Line Filter LF101 IC101 IC201 IC301 23mH IC FSCM0765RC KA431(TL431) H11A817A FPSTM(7A,650V) Voltage reference Opto-coupler Wire 0.4mm Bridge Diode
C101 C102 C103 C104 C105 C106 C201 C202 C203 C204 C205
220nF/275VAC 220nF/275VAC 100uF/400V 10nF/1kV 22uF/50V 47nF/50V 1000uF/25V 1000uF/25V 1000uF/10V 1000uF/10V 47nF/50V
Box Capacitor Box Capacitor Electrolytic Capacitor Ceramic Capacitor Electrolytic Capacitor Ceramic Capacitor Electrolytic Capacitor Electrolytic Capacitor Electrolytic Capacitor Electrolytic Capacitor Ceramic Capacitor
16
FSCM0765R
7. Layout
Figure 11. Layout Considerations for FSCM0765RC
Figure 12. Layout Considerations for FSCM0765RC
17
FSCM0765R
Package Dimensions
D2-PAK-5L
18
FSCM0765R
Package Dimensions (Continued)
TO-220-5L(Forming)
19
FSCM0765R
Ordering Information
Product Number FSCM0765RD FSCM0765RCYDTU Package D2-PAK-5L TO-220-5L Marking Code CM0765RD CM0765RC BVdss 650V 650V Rds(on)Max. 1.6 1.6
20
FSCM0765R
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 10/18/04 0.0m 001 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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